gaoxu
d7f7f0ad24
fix(adc): fix adc1 error after bootloader random
2024-12-31 11:28:28 +08:00
C.S.M
d448c4ed05
feat(spi_flash): Add 32M flash support on esp32c5
2024-12-25 16:06:43 +08:00
Armando
b963c0f013
feat(adc): supported adc calibration on esp32c5
2024-12-19 12:12:30 +08:00
Gao Xu
7ff0a07d3d
Merge branch 'feat/h21_introduce_step2_3' into 'master'
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feat(esp32h21): add soc register header files (stage 2/8, part 3/3)
See merge request espressif/esp-idf!35492
2024-12-14 18:58:14 +08:00
gaoxu
07862cf93e
feat(esp32h21): fix soc file and add soc files from verification branch (stage 2-3)
2024-12-14 17:08:19 +08:00
Guillaume Souchere
c80ba4023d
Merge branch 'fix/heap-allocate-in-rtc-iram' into 'master'
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fix(heap): MALLOC_CAP_EXEC does not allocate in RTC IRAM
Closes IDFGH-14012
See merge request espressif/esp-idf!34750
2024-12-12 18:51:52 +08:00
Konstantin Kondrashov
1937ef2b13
Merge branch 'fix/fix_coverity_issues' into 'master'
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fix(system): Fixes some false-positive coverity issues
Closes IDF-11768, IDF-11760, and IDF-11740
See merge request espressif/esp-idf!35288
2024-12-12 15:47:40 +08:00
Armando
6528ab5971
refactor(mspi): refactor mspi clock src settings
2024-12-11 14:46:07 +08:00
Guillaume Souchere
a995a5339b
fix(heap): MALLOC_CAP_EXEC does not allocate in RTC IRAM
...
This commit fixes the issue when trying to allocate memory
with the MALLOC_CAP_EXEC in RTC memory. Prior to the fix,
the heap allocator was returning an address in RTC DRAM.
To fix this issue:
- modified memory_layout.c of the concerned targets to fill the iram_address
field in the rtc entry of the soc_memory_region array properly.
- modified heap component related functions to return IRAM address when
an allocation in RTC memory with MALLOC_CAP_EXEC is requested.
Closes https://github.com/espressif/esp-idf/issues/14835
2024-12-09 09:34:56 +01:00
Konstantin Kondrashov
ad38ba16dd
fix(bootloader_support): Fix overflowed constant in process_segment
2024-12-05 15:10:27 +08:00
Konstantin Kondrashov
5a245a389b
fix(bootloader_support): Fix overflowed constant in bootloader_sha256_flash_contents
2024-12-05 15:10:27 +08:00
C.S.M
2b1c27feb4
Merge branch 'feat/custom_flash_component' into 'master'
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feature(spi_flash): New customized flash drivers framework, including bootloader📡
Closes IDFGH-8624
See merge request espressif/esp-idf!32774
2024-12-04 18:05:58 +08:00
Mahavir Jain
6a4a124d65
Merge branch 'feature/enable_rsa_based_secure_boot_for_c5_eco1' into 'master'
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feat(bootloader_support): enabled RSA based secure boot scheme for ESP32C5 ECO1
Closes IDF-10453 and IDF-11441
See merge request espressif/esp-idf!35104
2024-12-04 18:00:34 +08:00
Mahavir Jain
30dbc69428
Merge branch 'feat/enable_pseudo_rounds_function_in_aes' into 'master'
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Enable pseudo rounds function in AES and XTS-AES peripherals
Closes IDF-11305
See merge request espressif/esp-idf!33970
2024-12-04 13:48:09 +08:00
nilesh.kale
1e11340061
feat(bootloader_support): enabled RSA based secure boot scheme for ESP32C5 ECO1
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This commit enabled RSA based secure boot scheme for ESP32C5 ECO1 module.
This update also adds a check to ensure the selected secure boot scheme is
valid for ECO0 modules.
2024-12-03 16:48:56 +05:30
Song Ruo Jing
547fa88a44
Merge branch 'bugfix/periph_clk_init_p4' into 'master'
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fix(esp_system): hp periph clk should not be gated on core/system reset
Closes FCS-1638
See merge request espressif/esp-idf!35317
2024-12-03 15:45:28 +08:00
harshal.patil
f02dc64ce6
feat(bootloader_support): Permanently enable pseudo rounds function for XTS-AES during start-up
2024-12-03 11:17:54 +05:30
C.S.M
af31ec11f1
feat(spi_flash): New customise flash drivers framework, including bootloader
2024-12-02 17:48:40 +08:00
Laukik Hase
54c3f1bae4
feat(esp_tee): Support for ESP-TEE - bootloader_support component
2024-12-02 12:20:03 +05:30
Song Ruo Jing
7b852faf66
fix(esp_system): hp periph clk should not be gated on core/system reset
2024-11-29 21:42:06 +08:00
Armando (Dou Yiwen)
4cb18200d5
Merge branch 'feat/120m_flash_p4' into 'master'
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flash: 120MHz timing tuning support on ESP32P4 (no merge now)
Closes IDF-11678
See merge request espressif/esp-idf!34995
2024-11-29 11:40:29 +08:00
Armando
5237876213
flash: fix qio 2nd bootloader cannot boot issue
2024-11-28 14:53:20 +08:00
zlq
225c0513f5
fix(H2):fix pll low temp bug
2024-11-27 17:52:34 +08:00
laokaiyao
13f7b55ae5
change(soc): update lp_ana_peri soc header on C5
2024-11-26 11:14:57 +08:00
Gao Xu
bbcfb35d67
Merge branch 'feat/h21_introduce_step1_target' into 'master'
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feat(esp32h21): introduce target esp32h21 (stage 1/8) 😐
See merge request espressif/esp-idf!34542
2024-11-14 10:46:44 +08:00
Konstantin Kondrashov
52f14f344d
feat(partition_table): Support recovery bootloader subtype
2024-11-12 17:22:53 +08:00
gaoxu
64bbb53b8f
feat(esp32h21): introduce target esp32h21(stage 1)
2024-11-12 15:42:27 +08:00
Laukik Hase
19ab0213d9
change(bootloader): Map only the necessary length when fetching the app description struct
2024-11-07 18:13:53 +05:30
Mahavir Jain
4c6cda734d
Merge branch 'feature/mmu_page_size_from_app_bin' into 'master'
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feat(bootloader): add support to use MMU page size from app binary
Closes IDF-8209
See merge request espressif/esp-idf!33989
2024-11-06 17:14:31 +08:00
Mahavir Jain
afa46c06a8
feat(bootloader): add support to use MMU page size from app binary
...
For the SoCs that support configurable MMU page size, it is possible
that the bootloader and application are built with different MMU page
size configuration. This mismatch is not supported at the moment and
application verification fails (at bootup or during OTA update).
Configuring MMU page size helps to optimize the flash space by having
smaller alignment and padding (secure) requirements. Please note that
the MMU page size is tied with the flash size configuration at the
moment (`ESPTOOLPY_FLASHSIZE_XMB`).
This MR ensures that application verification happens using the MMU page
size configured in its binary header. Thus, bootloader and application
can now have different MMU page sizes and different combinations shall
be supported.
2024-11-05 20:37:18 +05:30
Song Ruo Jing
2cb35a2955
refactor(regi2c): ana i2c master clock is enabled per request
2024-11-04 12:37:17 +08:00
Song Ruo Jing
92ed77933b
refactor(clk): deprecate SOC_RTC_FAST_CLK_SRC_XTAL_DIV
2024-11-04 12:37:17 +08:00
Konstantin Kondrashov
8c4f576f99
feat(partition_table): Support primary subtypes partitions
2024-10-31 13:16:01 +02:00
Omar Chebib
908e1e670a
test(bootloader_support): enable analog super wdt reset for the ESP32-C61
2024-10-31 10:11:44 +08:00
Aditya Patwardhan
82db0feab2
fix(security): Update key manager specific initializations for esp32c5
2024-10-28 11:13:43 +08:00
C.S.M
ad6f491459
patch(spi_flash): cleanup XMC flash chip usage according to new information
2024-10-18 10:26:26 +08:00
Jiang Jiang Jian
88317cff24
Merge branch 'feat/pwr_glitch_bringup_c5_c61' into 'master'
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feat(pwr_glitch): Add power glitch reset support on esp32c5, esp32c61
See merge request espressif/esp-idf!33032
2024-10-15 14:15:49 +08:00
zhoupeng
858d0647e8
fix(pwr_glitch): Add Comment and only add power glitch reset support on esp32c5 ECO0
2024-10-09 11:08:38 +08:00
chaijie@espressif.com
e1423c53d5
feat(pwr_glitch): Add power glitch support on esp32c5/esp32c61
2024-10-08 11:44:21 +08:00
Konstantin Kondrashov
d5f37b526d
feat(partitions): Adds new partition types and subtypes for bootloader and partition_table
2024-10-01 14:22:22 +03:00
Mahavir Jain
336f938110
fix(bootloader): self encryption workflow in bootloader not working on C5
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Added explicit wait for key manager state to be idle before configuring
the register for flash encryption key usage from efuse. This now ensures
that flash contents are encrypted using efuse programmed key.
Also refactored code a bit to move into target specific directory.
2024-09-25 14:21:16 +05:30
C.S.M
75e2d77b26
feat(spi_flash): Add new xmc chip id
2024-09-23 19:06:23 +08:00
Mahavir Jain
a71e0fc028
Merge branch 'feature/enable_sha_support_for_esp32c61' into 'master'
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feat: enable support for sha peripheral in esp32c61
Closes IDF-9234
See merge request espressif/esp-idf!32830
2024-09-20 13:22:14 +08:00
Sachin Billore
b4749b88d9
feat(APM): Add APM APIs for ESP32-C61
2024-09-19 11:07:42 +05:30
Konstantin Kondrashov
e8dab4c257
Merge branch 'feature/esp32c61_update_efuses' into 'master'
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feat(efuse): Updates efuse table for esp32c61
Closes IDF-11057 and IDF-9282
See merge request espressif/esp-idf!33436
2024-09-12 01:20:20 +08:00
nilesh.kale
12fc7a677e
feat: enable support for sha peripheral in esp32c61
2024-09-11 14:49:01 +05:30
wuzhenghui
05e74480f5
feat(esp_system): gate some clock by default to optmize esp32p4 active power
2024-09-11 10:53:00 +08:00
Konstantin Kondrashov
8539760e79
feat(efuse): Updates efuse table for esp32c61
2024-09-10 14:16:29 +03:00
Armando
9c81fe6114
fix(mspi): fixed mspi clock wrong on ram loadable app on c61, enable tests on c5 c61
2024-09-10 11:12:03 +08:00
Armando
42cf1d8867
fix(mspi): fixed mspi clock wrong on ram loadable app on c5
2024-09-10 11:12:02 +08:00
